It is common practice in the art of recording data onto a recording medium and decoding data from a recording medium to use a voltage-controlled oscillator as the master clock pulse source. In the decoding operation, it is considered desirable to have the system operate as a self-clocking system. In such a mode, the ONES, or flux translations, on the recording medium, provide signals to a phase lock loop voltage controlled oscillator circuit to cause the voltage controlled oscillator to be in phase with signals coming from the recording medium. Heretofore, the phase synchronization has been accomplished by transmitting a preamble pattern of signals from the recording medium and at the end of the preamble pattern, the system was considered to be in phase synchronization. The preamble pattern has generally been considered to be without error. As the state of the art, with respect to bit packing and speed of the recording medium, has advanced, there have been errors in preamble patterns such as missing bits or spurious bit signals. Accordingly, the phase correction of the phase lock loop voltage controlled oscillator circuit has not been, at times, satisfactory. Further, if the system employs the preamble pattern as a means for defining word boundaries, in coding and decoding variable length words, then the phase locking of the word boundary clock pulse generator with the preamble pattern of signals is very important.
The present system mitigates the problems arising with missing bit signals and spurious bit signals related to a preamble pattern.